It is well known in the art to isolate regions of silicon from one another on a silicon substrate for the purpose of making active devices in the isolated regions. The most recent techniques for doing this involve isolating a layer of silicon vertically from an underlying silicon substrate with a dielectric layer, (commonly referred to as silicon on insulator or SOI). The advantages of having silicon devices on an insulator over bulk silicon substrates are that it provides higher packing density due to better isolation properties, simplified fabrication technology, radiation hardened capabilities, higher speeds due to fully depleted structures, and higher latch-up immunity. The above mentioned advantages to silicon on insulator structures are somewhat off set, however, by heat dissipation problems due to the fact that the isolating insulators have both a low electrical conductivity and low thermal conductivity. Poor power dissipation therefore imposes a considerable constraint for development of high speed/high power circuits on the isolated silicon regions.
A technique which resolves these thermal dissipation problems by providing a high thermal conductive path from the isolated silicon regions to the underlying silicon substrate is therefore highly desirable.